`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 		PI3
// Engineer: 		Matthias Niethammer
// 
// Create Date:    17:31:33 10/15/2010 
// Design Name: 
// Module Name:    reg_counter_up
// Project Name: 
// Target Devices: 
// Tool versions:	ISE 11.1
// Description: 	register based upward counter with variable width and overflow flag 
//
// Dependencies: 	none
//
// Revision: 
// Revision 0.03 - additional upward labeling
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module reg_counter_up # (parameter N = 10, OVER = 0) (
    input clk,
    input enable,
    input reset,
    output [N-1:0] out,
    output overflow
    );


reg [N-1:0] temp;
reg over;
assign out[N-1:0] = temp[N-1:0];
assign overflow = over;

always@( posedge clk , posedge reset)
begin

		if( reset )
		begin
			temp <= 0;
			over <= 0;
		end
		else if ( enable)
		begin
			temp <= temp + 1;
			if( temp == OVER )
				over <= 1;
			else
				over <= 0;
		end
end
			
endmodule
